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Smart Structures and Systems
  Volume 14, Number 6, December 2014, pages 1131-1150

Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system
Akira Igarashi

    One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.
Key Words
    real-time processing; fast computing; parallel processing; logic circuit
Akira Igarashi: Disaster Prevention Research Institute, Kyoto University, Gokasho, Uji-shi, Kyoto 611-0011 Japan

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